|1.Research Institution||Osaka University|
|2.University-Industry Cooperative Research Committee||165th Committee on Ultra Integrated Silicon Systems|
|3.Term of Project||FY 1999 - FY 2003|
|5.Title of Project||Research and Development of Code-division-multiple-access Data Bus and its Application for Intelligent Information Systems|
|Name||InstitutionCDepartment||Title of Position|
|Kenji,Taniguchi||Osaka University, Graduate School of Engineering||Professor|
|Names||Institution,Department||Title of Position|
|Kazuo,Tsubouchi||Tohoku University, Research Institute of Electrical Communication||Professor|
|Hiroto,Yasuura||Kyushu University, Graduate School of Information Science and Electrical Engineering||Professor|
|Tadashi,Nishimura||Renesas Technology Corp.||Managing Officer|
8.Summary of Research Results
The aim of this research is development of new interface technology and its application to overcome von Neumann bottleneck, the most serious problem in today's information systems. We have proposed a new multiple access interface technology based on CDMA (Code-Division-Multiple-Access) technique. This technology has the following features: 1) reduction of the wiring number in system LSI, 2) low voltage swing data transfer with enough noise tolerance, and 3) achievement of new parallel data processors without von Neumann bottleneck.
The results of this research are as follows,
1) Wired CDMA Interface
The interface circuits for wired CDMA bus were implemented in small size (0.1mm x 0.1mm) using 0.6 m CMOS technology. The fabricated chip demonstrated error-free operation for 108 data transfers. To achieve efficient design of CDMA interface circuits, the behavior-level simulation technique has been developed. In addition, multiple-bit CDMA interface and parallel CDMA interface have been proposed to increase data rate.
2) Wireless CDMA Interface
Based on our trial wireless circuit design, a new modulation/demodulation scheme for wireless CDMA interface, ASK/CDMA technique, has been developed. The transmitter and receiver for wireless ASK/CDMA interface with a carrier frequency of 10GHz and an M-sequence of 250Mcps were implemented in 0.25 m CMOS technology. The fabricated chip demonstrated feasibility of the wireless ASK/CDMA data transfer.
3) Fundamental Circuit Techniques
Some techniques required to develop the CDMA interface have been studied as follows: 1) Device Parameter Extraction (MOSFET's Mismatch, SOI Device, and On-chip Inductor), 2) Voltage reference, Pipelined A/D Converter, and Correlator, and 3) Voltage Controlled Oscillator, Predistorter, and PLL Duty-Cycle Correction Circuit.
4) Application of Wired CDMA Interface
Using wired CDMA interface, Dynamically Programmable Arithmetic Array (DPAA) and Dynamically Programmable Parallel Processor (DPPP) have been developed. The main feature of these information systems is dynamic reconfiguration of wiring topology.