Summary of Research Project Results under JSPS FY2002
"Research for the Future Program"

1.Research Institution The University of Tokyo
2.University-Industry Cooperative Research Committee 165th Committee on Ultimately Integrated Devices and Systems
3.Term of Project FY 1998 - FY 2002
4.Project Number 98R16501
5.Title of Project Research on Ultra Low-power System LSI Technology

6.Project Leader
Name Institution,Department Title of Position
Takayasu, Sakurai The University of Tokyo, Center for Collaborative Research Professor

7.Core Members

Name Institution,Department Title of Position
Toshiro, Hiramoto The University of Tokyo, Institute of Industrial Science Professor
Hidetoshi, Onodera Kyoto University, Graduate School of Informatics Professor

8.Summary of Research Results

  In this study, supply voltage hopping was proposed to reduce power consumption on multi-task environment for multi-media applications. And a 0.5V, 400MHz, voltage hopping processor with FD-SOI Technology was designed and measured. If supply voltage was about 0.8V, sub-threshold leak power could be reduced by DIBL(Drain Induced Barrier Lowering) with variation supply voltage in the region of leakage power dominant. Therefore, VDD hopping is effective near future some years and VTH hopping will be effective after that. To reduce leakage current is important for memories. A dual VDD method which used high supply voltage and threshold voltage for memory cell and a Row-by-row method which varies VDD and VSS during memory access ware proposed. Both of the method achieved 2 or 3 orders of leakage current was reduced.

  From device side, a new device and circuit scheme named Boosted Gate MOS(BGMOS) that suppress the stand-by leakage current was proposed. Applying boosted gate voltage on the low leakage switches with higher VTH and thicker gate oxide. On the other hand, variable threshold CMOS(VTCMOS) with large body effect factor devices will maintain its advantage in the future. We have been systematically investigated and clarified by means of device simulation and fabrication.

  In order to design high yield product, we must consider not only inter-chip variability but also intra-chip variability of device characteristics. In this study, we propose a modeling and extracting methodology of both variabilities. We therefore extract model parameters of intra-chip variability from the measured current directly. A simple intermediate model is introduced to eliminate model dependency of parameter estimation for numerical optimization techniques. Furthermore, we made a model of delay variability and analyzed effect of intra-chip variability to delay of logic gates. Hereby, gate level analysis of static delay with considering intra-chip variability was achieved.

9.Key Words
(1)low-power   (2)integrated circuit   (3)modeling
(4)design of device   (5)variability   (6)LSI
(7)scaling   (8)processor   (9)leakage current